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Planche 2 |
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Planche 3 |
| 09-30 | JJL | shared memory atomicity, SOS |
| 10-07 | JJL | shared memory readers/writers, 5 philosophers |
| 10-12 | PLC | CCS choice, strong bisim. |
| 10-21 | PLC | CCS weak bisim., examples |
| 10-28 | PLC | CCS obs. equivalence, Hennessy-Milner logic |
| 11-04 | PLC | CCS examples of proofs |
| 11-16 | JL | p-calculussyntax, lts, examples, strong bisim. |
| 11-25 | JL | p-calculusred. semantics, weak bisim., congruence |
| 12-02 | JL | p-calculusextensions for mobility |
| 12-09 | JL/CP | p-calculusencodings: l-calculus, arithm., lists |
| 12-16 | CP | p-calculusexpressivity |
| 01-06 | CP | p-calculusstochastic models |
| 01-13 | CP | p-calculussecurity |
| 01-20 | EG | true concurrency concurrency and causality |
| 01-27 | EG | true concurrency Petri nets, events struct., async. trans. |
| 02-03 | EG | true concurrency other models |
| 02-10 | all | exercices |
| 02-17 | exam |
Planche 4 |
Planche 5 |
Planche 6 |
Planche 7 |
Planche 8 |
P0 : ··· while turn != 0 do ; C0; turn := 1; ··· |
P1 : ··· while turn != 1 do ; C1; turn := 0; ··· |
Planche 9 |
P0 : ··· while a1 do ; a0 := true; C0; a0 := false; ··· |
P1 : ··· while a0 do ; a1 := true; C1; a1 := false; ··· |
P0 : ··· a0 := true; while a1 do ; C0; a0 := false; ··· |
P1 : ··· a1 := true; while a0 do ; C1; a1 := false; ··· |
Planche 10 |
P0 : ··· a0 := true; while a1 do if turn != 0 begin a0 := false; while turn != 0 do ; a0 := true; end; C0; turn := 1; a0 := false; ··· |
P1 : ··· a1 := true; while a0 do if turn != 1 begin a1 := false; while turn != 1 do ; a1 := true; end; C1; turn := 0; a1 := false; ··· |
Planche 11 |
P0 : ··· a0 := true; turn := 1; while a1 && turn != 0 do ; C0; a0 := false; ··· |
P1 : ··· a1 := true; turn := 0; while a0 && turn != 1 do ; C1; a0 := false; ··· |
Planche 12 |
··· {¬ a0 Ù c0¹ 2 } 1 a0 := true; c0 := 2; {a0 Ù c0 = 2} 2 turn := 1; c0 := 1; {a0 Ù c0 ¹ 2} 3 while a1 && turn != 0 do . ; {a0 Ù c0¹ 2 Ù (¬ a1 Ú turn= 0 Ú c1 = 2)} . C0; 5 a0 := false; {¬ a0Ù c0¹ 2} ··· |
··· {¬ a1 Ù c1¹ 2 } a1 := true; c1 := 2; {a1 Ù c1 = 2} turn := 0; c1 := 1; {a1 Ù c1 ¹ 2} while a0 && turn != 1 do ; {a1 Ù c1¹ 2 Ù (¬ a1 Ú turn= 1 Ú c0 = 2)} C1; a1 := false; {¬ a1Ù c1¹ 2} ··· |
Planche 13 |
| (turn= 0 Ú turn= 1) | |
| Ù | a0 Ù c0¹ 2 Ù (¬ a1 Ú turn= 0 Ú c1 = 2) Ù a1 Ù c1¹ 2 Ù (¬ a0 Ú turn= 1 Ú c0 = 2) |
| º | (turn= 0 Ú turn= 1) Ù tour = 0 Ù tour = 1 Impossible |
Planche 14 |
··· {¬ a0 Ù c0¹ 2 } 1 a0 := true; c0 := 2; {a0 Ù c0 = 2} 2 turn := 1; c0 := 1; {a0 Ù c0 ¹ 2} 3 while a1 && turn != 0 do . ; {a0 Ù c0¹ 2 Ù (¬ a1 Ú turn= 0 Ú c1 = 2)} . C0; 5 a0 := false; {¬ a0Ù c0¹ 2} ··· |
··· {¬ a1 Ù c1¹ 2 } a1 := true; c1 := 2; {a1 Ù c1 = 2} turn := 0; c1 := 1; {a1 Ù c1 ¹ 2} while a0 && turn != 1 do ; {a1 Ù c1¹ 2 Ù (¬ a1 Ú turn= 1 Ú c0 = 2)} C1; a1 := false; {¬ a1Ù c1¹ 2} ··· |
Planche 15 |
| (turn= 0 Ú turn= 1) | |
| Ù | a0 Ù c0¹ 2 Ù (¬ a1 Ú turn= 0 Ú c1 = 2) Ù a1 Ù c1¹ 2 Ù (¬ a0 Ú turn= 1 Ú c0 = 2) |
| º | (turn= 0 Ú turn= 1) Ù tour = 0 Ù tour = 1 Impossible |
Planche 16 |
Planche 17 |
| acquire(s): If s > 0 then s := s-1. Otherwise restart. |
| release(s): Do s := s+1. |
Planche 18 |
| P,Q | ::= | skip | x := e | if b then P else Q | P;Q | while b do P | · |
| e | ::= | expression |
| á skip , s ñ ® á ·, s ñ | á x := e, s ñ ® á ·, s[s(e)/x] ñ | |||||||||||
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Planche 20 |
| á P0, s0 ñ ®* á Pn, sn ñ when n ³ 0, |
| á P0, s0 ñ ®+ á Pn, sn ñ when n > 0. |
| s(e) = false | |
| á wait e, s ñ ® á wait b, s ñ |
Planche 21 |
| á P, s ñ ®+ á ·, s' ñ | |
| á {P}, s ñ ® á ·, s' ñ |
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Planche 23 |
INTERFACE Thread; TYPE T <: ROOT; Mutex = MUTEX; Condition <: ROOT;A Thread.T is a handle on a thread. A Mutex is locked by some thread, or unlocked. A Condition is a set of waiting threads. A newly-allocated Mutex is unlocked; a newly-allocated Condition is empty. It is a checked runtime error to pass the NIL Mutex, Condition, or T to any procedure in this interface.
Planche 24 |
PROCEDURE Acquire(m: Mutex);Wait until m is unlocked and then lock it.
PROCEDURE Release(m: Mutex);The calling thread must have m locked. Unlocks m.
PROCEDURE Wait(m: Mutex; c: Condition);The calling thread must have m locked. Atomically unlocks m and waits on c. Then relocks m and returns.
PROCEDURE Signal(c: Condition);One or more threads waiting on c become eligible to run.
PROCEDURE Broadcast(c: Condition);All threads waiting on c become eligible to run.
Planche 25 |
LOCK mu DO S END
where S is a statement and mu is an
expression. It is equivalent to:
WITH m = mu DO
Thread.Acquire(m);
TRY S FINALLY Thread.Release(m) END
END
where m stands for a variable that does
not occur in S.Planche 26 |
TRY S_1 FINALLY S_2 END
executes statement S1 and then
statement S2. If the outcome of S1 is
normal, the TRY statement is equivalent
to S1;S2. If the outcome of S1 is an
exception and the outcome of S2 is
normal, the exception from S1 is
re-raised after S2 is executed. If both
outcomes are exceptions, the outcome of
the TRY is the exception from S2.Planche 27 |
VAR nonEmpty := NEW(Thread.Condition);
LOCK m DO
WHILE p = NIL DO Thread.Wait(m, nonEmpty) END;
topElement := p.head;
p := p.next;
END;
return topElement;
Pushing into a stack:
LOCK m DO
p = newElement(v, p);
Thread.Signal (nonEmpty);
END;
Caution: WHILE is safer than IF in Pop.Planche 28 |
VAR table := ARRAY [0..999] of REFANY {NIL, ...};
VAR i:[0..1000] := 0;
PROCEDURE Insert (r: REFANY) =
BEGIN
IF r <> NIL THEN
table[i] := r;
i := i+1;
END;
END Insert;
Exercice 12 Complete previous program to avoid lost values.Planche 29 |
Planche 30 |
Wait (m, c) : release(m); acquire(c-sem); acquire(m); |
Signal (c) : release(c-sem); |
Planche 31 |
This document was translated from LATEX by HEVEA.