 be the set of possible CPU
states, the CPU acts like a deterministic function
 be the set of possible CPU
states, the CPU acts like a deterministic function  . According to this model, to each state
. According to this model, to each state  there corresponds
a next state
 there corresponds
a next state  . The rate at which the CPU changes state is
governed by the system clock (usual rates are between 1 and 3
GHz). Thus, around every billionth of a second, the CPU changes its
state.
. The rate at which the CPU changes state is
governed by the system clock (usual rates are between 1 and 3
GHz). Thus, around every billionth of a second, the CPU changes its
state. 
The form of the function  obviously depends on the CPU make and
model. CPUs usually contain some extremely fast but very small memory
chunks called ``registers'' which are specifically designed to store
either values or memory addresses. The state of the CPU at each clock
tick is then determined by the values contained in each of its
registers. The CPU is designed in such a way that at each clock tick
the memory address contained in a certain register will automatically
be incremented, and the value contained at the new address is read and
interpreted as a ``machine code instruction''. This allows us to
interpret the function
 obviously depends on the CPU make and
model. CPUs usually contain some extremely fast but very small memory
chunks called ``registers'' which are specifically designed to store
either values or memory addresses. The state of the CPU at each clock
tick is then determined by the values contained in each of its
registers. The CPU is designed in such a way that at each clock tick
the memory address contained in a certain register will automatically
be incremented, and the value contained at the new address is read and
interpreted as a ``machine code instruction''. This allows us to
interpret the function  in a different way: we can consider the
next state
 in a different way: we can consider the
next state  of the CPU as given by a function
 of the CPU as given by a function 
 with
with  , where
, where  is a machine code instruction in the set
 is a machine code instruction in the set
 of all possible CPU instructions. Although each basic instruction
in
 of all possible CPU instructions. Although each basic instruction
in  is rather simple, this interpretation of
 is rather simple, this interpretation of  makes it possible
to group several simple instructions into more complex
ones1. As some of the instructions
concern logical tests and loops, it becomes apparent that the full
semantics of any modern computer language (including C++) can indeed
be exploited by a CPU after a suitable transformation of the complex,
high-level language into the simple machine code instruction set
 makes it possible
to group several simple instructions into more complex
ones1. As some of the instructions
concern logical tests and loops, it becomes apparent that the full
semantics of any modern computer language (including C++) can indeed
be exploited by a CPU after a suitable transformation of the complex,
high-level language into the simple machine code instruction set  .
.
Loosely speaking, the set  can be partitioned in the following
instruction categories.
 can be partitioned in the following
instruction categories.
 (bits) it can
contain. Traditionally, on Intel 16-bit architectures (32- and 64- bit
architectures are evolutions thereof, and each new version is
guaranteed to retain backward compatibility) there are four
general-purpose registers: AX (accumulator), BX (base), CX (counter),
DX (data); four pointer registers: SI (source index), DI (destination
index), BP (base pointer), SP (stack pointer); four segment registers:
CS (code segment), DS (data segment), ES (extra segment), SS (stack
segment); and finally, one instruction pointer IP. The machine code
instruction
 (bits) it can
contain. Traditionally, on Intel 16-bit architectures (32- and 64- bit
architectures are evolutions thereof, and each new version is
guaranteed to retain backward compatibility) there are four
general-purpose registers: AX (accumulator), BX (base), CX (counter),
DX (data); four pointer registers: SI (source index), DI (destination
index), BP (base pointer), SP (stack pointer); four segment registers:
CS (code segment), DS (data segment), ES (extra segment), SS (stack
segment); and finally, one instruction pointer IP. The machine code
instruction  loaded at each clock tick to compute
 loaded at each clock tick to compute  is
the value found at the address CS:IP. More information can be found
at http://www.ee.hacettepe.edu.tr/~alkar/ELE414/ and 
http://ourworld.compuserve.com/homepages/r_harvey/doc_cpu.htm.
 is
the value found at the address CS:IP. More information can be found
at http://www.ee.hacettepe.edu.tr/~alkar/ELE414/ and 
http://ourworld.compuserve.com/homepages/r_harvey/doc_cpu.htm.
Consider now the following (informal) definitions:
Leo Liberti 2008-01-12